MathWorks Updates HDL Verifier

MathWorks has launched new capabilities in its HDL Verifier to speed up FPGA-in-the-Loop (FIL) verification. HDL Verifier for FIL verification automates the setup and connection of MATLAB and Simulink test environments to designs running on FPGA development boards. This helps to deliver high-fidelity co-simulations of the FPGA designs running on actual hardware, while reusing the same test environment used for development, the company states.

According to MathWorks, The R2016b release allows engineers to specify a custom frequency for their FPGA system clock, with clock rates up to five times faster than previously possible with FIL. And for designs that use overclocking factors when targeting an FPGA, such as control applications, larger data output sizes can be used to increase throughput.

Engineers can now utilize FIL (using the PCI Express interface) to speed up communications between MATLAB and Simulink, and Xilinx KC705/VC707 and Intel Cyclone V GT/Stratix V DSP development boards, with simulation speeds three to four times faster than Gigabit Ethernet.

“As electronic systems become more complex, the need to accurately prototype as a validation step becomes vital,” said Jack Erickson, product manager at MathWorks. “HDL Verifier now allows engineers to run designs on real hardware, at realistic clock frequencies, and with fast runtimes. Being able to do this from MATLAB and Simulink is an easy way to validate hardware design within the algorithm development environment.”

For more information, visit MathWorks.

Sources: Press materials received from the company and additional information gleaned from the company’s website.