Intel Foundry Collaborates with Cadence and Siemens

Cadence and Intel Foundry have collaborated to develop and certify an integrated advanced packaging flow utilizing Embedded Multi-die Interconnect Bridge (EMIB) technology to address the complexity in heterogeneously integrated multi-chip(let) architectures, the companies report. The collaboration enables Intel customers to leverage advanced packaging to accelerate the high-performance computing (HPC), AI and mobile computing design space.

The advanced EMIB flow enables design teams to transition from early-stage system-level planning, optimization and analysis to design rule checking-aware implementation and physical signoff without converting data between different formats. 

The joint effort has resulted in an advanced packaging flow, including Cadence’s Allegro X APD (for placement, signal/power/ground routing, in-design electrical analysis, DFM/DFA and final manufacturing output), Integrity 3D-IC Platform and Integrity System Planner (for system-level design aggregation, planning and optimization), Sigrity and Clarity solvers (for 3D EM extraction, two-parameter generation, early-stage and signoff signal integrity, DC/AC power analysis, and packaging model extraction), Celsius solvers (for early-stage and signoff thermal signoff/stress), Virtuoso Studio (for signal/power/ground routing of EMIB bridges), and Pegasus Verification System (for signoff DRC and SystemLVS).

“As more designers turn to multi-chiplet architectures and advanced packaging, there’s more emphasis on having the right design tools and methodologies,” says Michael Jackson, corporate vice president of Research and Development, Custom IC and PCB Group at Cadence. “The Cadence collaboration with Intel helps streamline this transition to heterogeneous integrated solutions by offering an EMIB-certified reference flow.”

“Incorporating thermal, signal integrity and power modeling early in engineering projects' planning and implementation stages is crucial for a seamless design process,” says Rahul Goyal, vice president and general manager, Product and Design Ecosystem, Intel Foundry. “By integrating these considerations upfront, engineers can conduct concurrent design and signoff activities, which help to avert potential downstream delays.”

In related news, Intel Foundry has also partnered with Siemens Digital Industries Software to develop a comprehensive workflow for the foundry’s EMIB approach to in-package, high-density interconnect of heterogeneous chips.

“Our collaboration with Siemens enables us to define a certified, production ready EMIB technology reference flow that we can deliver to our customers so that they can design efficiently and effectively,” says Rahul Goyal, vice president and general manager, Product and Design Ecosystem, Intel Foundry.

With this new Intel Foundry workflow, mutual customers can tackle a range of tasks including early package assembly prototyping, hierarchical device floorplanning, co-design optimization, verification of the complete detailed implementation, including signal and power integrity analysis, and Package Assembly Design Kit driven assembly verification. 

The Siemens technologies incorporated in this reference flow include Xpedition Substrate Integrator software, Xpedition Package Designer software, Hyperlynx software SI/PI and the Calibre nmPlatform tool including Calibre 3DSTACK software.

“Siemens is pleased to collaborate with Intel Foundry to develop and deliver a certified reference flow for Intel’s innovative EMIB technology,” says AJ Incorvaia, senior vice president, Electronic Board Systems, Siemens Digital Industries Software.“

Sources: Press materials received from the company and additional information gleaned from the company’s website.

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