Multi-Layer Integration for the IoT

The fundamental differences among these domains make the testing and verification of the designs one of the primary obstacles to bringing IoT devices to market quickly. What design engineers need now is a new set of design tools.

Interfacing the Analog and Digital Worlds

One area in need of tools: The design of complex mixed-signal systems. Concurrent verification of the analog and digital portions of a design has proven to be a major challenge. Mixed-signal design environments, however, have evolved to support true mixed-signal simulations, using event-based digital simulators and analog solvers to verify complete mixed-signal systems on chip. Even so, verifying top-level mixed-signal systems can be a problem because of the time it takes to run analog simulations, and all too often, this prevents design teams from getting chips into production on time.

Design packages like Cadence’s mixed-signal platform hope to address this issue using metric-driven, mixed-signal verification and standardized flow methodologies for generating and tracking verification coverage. This brings assertion-based verification to mixed-signal designs using automated analog behavioral modeling. The other piece of Cadence’s solution lies in its support of behavioral models of the analog portion of the designs, using Verilog-A or Verilog-AMS with real-number models.

To streamline the process of generating behavioral models, Cadence offers a schematic model generator that produces analog/mixed-signal behavioral models using a schematic-like representation. Designers can take the schematic view and generate the behavioral model in Verilog-AMS.

Working with MEMS

The design of MEMS devices also presents unique engineering challenges when it comes to integration with CMOS-based platforms. Engineers have to wrestle with issues like nonstandard fabrication processes, multiphysics interactions and packaging requirements. To make matters worse, traditional EDA (electronic design automation) tools simply do not have the resources to take on these challenges. This disconnect between the CMOS and MEMS design processes inevitably results in much longer development cycles.

MEMS designers have traditionally relied on the time-consuming and costly build-and-test approach. With the emergence of the IoT, developers of MEMS design automation software have adopted a view of integration that includes the processes required to combine MEMS with CMOS electronics. To this end, MEMS design software must deliver models compatible with the tools of choice for electronics design, such as MathWorks’ MATLAB and Simulink, and the Cadence Virtuoso suite.

An example of this can be seen in Coventor’s MEMS design platform. MEMS+6.0 offers second-generation model reduction, with the ability to export to MathWorks Simulink or the Verilog-A format. The resulting reduced-order models promise to simulate nearly as fast as handcrafted models, but far more accurately. This enables system designers to incorporate nonlinear MEMS device models in their system- and circuit-level simulations. Coventor has simplified the inputs for model reduction, and the platform automatically includes critical dynamic and electrostatic effects. In addition, MEMS+6.0 includes an expanded MATLAB scripting interface for design entry and simulation control.

With Coventor’s software, MEMS designers can combine ASICs (application-specific integrated circuits) and MEMS devices for full MEMS and IC (integrated circuit) simulation, producing a 3D model from the simulations augmented with details from FEA (finite element analysis). Designers can also run system simulations in the MATLAB/Simulink environment and perform co-simulations of sensor structure and sensing electronics by importing the MEMS+ model into Cadence Virtuoso.

Just the Beginning

While tools for analog, mixed-signal and MEMS design integration have begun to meet the needs rising from the emergence of the IoT, they are just that—a beginning. Design automation software vendors and fabrication process developers have miles to go before they sleep.