Mentor Graphics Updates Enterprise Verification Platform

Mentor Graphics has enhanced its Mentor Enterprise Verification Platform (EVP) to offer new levels of performance and productivity. This update sees improvements in the platform’s simulation, debugging, formal, coverage closure and low power verification functions.

The EVP Questa Simulation engine now runs up to four times faster with enhancements in both raw VHDL/Verilog performance and incremental flows, as well as a new checkpoint/restore/modify/run flow. The engine also has added native Questa fast logging technology that enables debug mode simulations to run faster and require three times less memory.

For low power applications, The Questa Power Aware Simulation is equipped with first-to-market support of IEEE 1801 UPF 2.1. It also includes automatic static and dynamic low power UPF checks and testplan generation. For debugging, the Visualizer Debug Environment has a complete set of windows to display UPF-generated structures, power domains, source/sync crossings, isolation, shifters and more.

“Our customers demand high-performance verification engines that achieve the fastest results in all facets of the verification flow: regression testing, debug and coverage,” said John Lenyo, vice president and general manager, Design Verification Technology Division, Mentor Graphics. “The Mentor Enterprise Verification platform delivers best-in-class performance, productivity and low power analysis in a single, integrated verification platform.”

For more information, visit Mentor Graphics.

Sources: Press materials received from the company and additional information gleaned from the company’s website.