Computing Technology

By John H. Hengeveld

Editor’s note: This commentary was sponsored as part of DE’s Visionary Voices section in the magazine’s15th anniversary issue.

Gordon Moore

Congratulations, Desktop Engineering, on 15 years of helping your community of readers see how hardware and software technologies combine to create revolutionary opportunities. Job well done; here is to 15 more.

  Today, silicon chips are everywhere. The task of making chips is no small feat. Designing them and the delivering the compute capacity demanded by our engineers is colossal. A modern “fab,” a building where Intel makes its chips, has close to 1 million sq. ft. of space and is among the most technically advanced manufacturing facilities in the world. Our engineers continue to add new features and new instructions to the tiny silicon “engines” that drive an ever expanding and connected digital world. These silicon chips are powering the Internet, enabling mobile computing, automating factories, enhancing cell phones, and are found in the workstations and high-performance computers (HPCs) that engineers employ to create tomorrow’s innovations. If you are wondering, it is estimated that about 10,000,000,000,000,000,000 (that’s 10 quintillion) transistors are now shipping each year—that’s about 100 times the number of ants estimated to be on Earth.

  Computing in 2025
Let’s look out 15 years. It’s where we’ll be in 15 years that shapes where we need to be in 5 years. Moore’s law will be still in place, and we will probably see manufacturing processes that support 4.5 nanometers (nm) or smaller. I expect workstations will support more than 28 Exaflops and the king of the hill in the HPC world will be approaching 1 Zetto flop. Today’s workstation delivers just over 150 Gflops.

  High fidelity, multi modality, full system design and modeling on Intel Xeon based systems will be the norm. Agent supported simulation-based design will probably be celebrating its 10th anniversary, and automated design mediators will augment our opportunity to create, test and modify ideas at speeds that could be real-time. The mouse will disappear, and things like electronic clay and other haptics technologies will emerge.

  Technologies that are employed to solve complex problems composed of computationally intensive applications will probably be accessible in ways you only dream of today. You may have access to greater functionality and control from your pocket. It will be available in your office and larger, higher fidelity models will leverage the resources of either corporate or cloud-based assets. I expect to see a compute continuum from handheld systems through HPCs that will provide fast,  efficient, easy and affordable access to compute capacities. If you need an immediate answer, you may use the cloud. If you can wait, you will use other resources that will provide more affordable results in an acceptable timeframe.

  The Way Forward
There is no magic to delivering solutions found in workstations and HPCs. It is centered on delivering a balanced computing architecture that provides processing performance, memory and bandwidth capacity. It is the three-legged stool story. If the compute capacity outstrips the facility to access and store data, you end up with subpar performance. The way forward is through increased levels of integration enabled by manufacturing processes ensconced in Moore’s law. Here is a near-term example: For years, CAD users looked to discrete add-in professional graphics cards to supply the performance they demanded to do CAD. However, integrated and optimized graphics solutions in 2011 on Intel Xeon processor-based workstations are expected to meet the demands of many 2D and 3D CAD applications in an even more energy-efficient design.

  As the industry traverses from 32nm manufacturing technologies to 22, 18, to 12 onto 9, 6.5 and eventually to 4.5nm, expect to see not only more cores, but more cores that each process more instruction per cycle—that is a multiplier effect. Remember the three-legged stool. You can also expect to see heterogeneous architectures that combine vector, scalar and graphics architectures with new memory topologies and i/o infrastructures.

  Back to the 5-year outlook:  You will see increased levels of hardware integration and most likely the introduction of heterogeneous architectures that will deliver an unbelievable amount of performance from a balanced computing architecture. The trick is helping the ecosystem realize this performance without requiring vendor-specific software that limits end-user choice. Software needs to be portable and scalable to realize the vision of a design environment with access to agent supported simulation-based design or automated design mediators.

John H. Hengeveld is director of Technical Computing Marketing, Intel Architecture Group.