Blue Pearl Announces Release 6.0 of EDA Software Suite

By DE Editors

Blue Pearl Software is shipping Release 6.0 of its Blue Pearl Software Suite EDA software for Windows and Linux operating systems. It includes enhancements that improve support for SystemVerilog and VHDL, as well as FPGA design.
 
Our 6.0 Release improves support for SystemVerilog and VHDL and the FPGA synthesis flow, said Shakeel Jeeawoody, director of product marketing at Blue Pearl. Designers can now mix and match hardware languages in the same design, with language checking that matches their downstream tools.
 
The software offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC)  generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated timing constraints.

For more information, visit Blue Pearl Software.

Sources: Press materials received from the company and additional information gleaned from the company’s website.