Apache Design Releases Redhawk for Sub-20 Nanometer Power Sign-off

By DE Editors

ANSYS subsidiary Apache Design introduced its RedHawk 3DX fourth-generation power sign-off solution, which delivers greater accuracy, capacity and usability for full-chip dynamic power and reliability simulation to manage power consumption and improve power delivery efficiency of advanced integrated circuit (IC) designs.

The new release previous generations capabilities to address sub-20 nanometer (nm) designs with 3-plus Ghz performance and billions of gates. It is also architected to support the simulation of emerging chip and packaging technologies using multi-die three-dimensional ICs (3D-ICs) for smart electronic products.

The new release improves the accuracy and coverage of dynamic power analysis by providing enhanced logic-handling capabilities. Its new event- and state-propagation technologies with vector-based and VectorLess modes utilize both the functional stimulus and statistical probability to determine the switching scenario of the design. The fast event-propagation engine uses register transfer language (RTL)-level functional stimulus to perform cycle-accurate voltage drop simulation. The state-propagation engine for the VectorLess mode enables time-domain transient analysis without actual input stimulus and includes proprietary techniques to eliminate underestimation of toggle rates associated with traditional activity-based propagation approaches. RedHawk-3DX also supports flexible mixed-excitation mode,  in which some blocks use RTL or gate-level vectors while the rest of the design uses the VectorLess methodology.

The new extraction reuse view (ERV) technology optimizes a majority of the design while allowing selected critical blocks to retain full-layout details, enabling full-chip simulation with complete consideration for package impact.

Emerging chip and packaging technologies for stacked-die, 3D-IC architecture help to reduce IC power consumption. The new release provides a 3D-IC extension to support both concurrent and model-based multi-die simulations of designs with silicon interposer and through-silicon vias (TSVs). The concurrent mode enables simulation of all chips including the interposer in full layout detail, whereas a model-based approach allows the use of a Chip Power Model (CPM) for some of the chips.

For more information, visit Apache Design and ANSYS.

Sources: Press materials received from the company and additional information gleaned from the company’s website.