Accellera Approves Universal Verification Methodology (UVM) Standard

By DE Editors

Accellera,  the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) standards and intellectual property (IP) standards, has approved version 1.0 of its Universal Verification Methodology (UVM) standard.

This standard, developed by Accellera’s Verification IP (VIP) Technical Subcommittee (TSC), is available as a Class Reference Manual accompanied by an open-source SystemVerilog base class library implementation and a user guide. The UVM standard establishes a methodology to improve design and verification efficiency, verification data portability, and tool and VIP interoperability.

The UVM Class Reference Manual is available for no cost.

“This is a significant accomplishment because the new features were complex and required considerable effort to build from a full list of requirements,” says Hillel Miller, co-chair, Accellera’s VIP TSC. “The committee reconciled the requirements list, agreed to a specification,  implemented them and tested the results in an effort that coordinated hundreds of people across several continents.”

UVM 1.0 leverages features from the baseline UVM 1.0 Early Adopter (EA) release, a direct derivative of the Open Verification Methodology (OVM). This allowed the Accellera VIP TSC to focus on adding features found in other common methodologies to satisfy the agreed functional requirements to shorten the standards development cycle.

At its Design Verification Conference and Exposition (DVCon), Accellera is sponsoring a workshop to unveil UVM on Monday, February 28, 2011.

For more information, visit Accellera.

Sources:  Press materials received from the company and additional information gleaned from the company’s website.